The present application relates to power factor correction circuits, that is, circuits for reducing the distortion and harmonics generated in a power line feeding a power supply, and in particular a switch mode power supply to make the circuit, including the attached load appear to be a substantially resistive load. More specifically, the present application relates to a control circuit for use in digital control of a power factor correction circuit to ensure that the AC voltage and current are substantially in phase which improves efficiency and at the same time eliminates the generation of harmful harmonics.
FIG. 1 illustrates a conventional boost power factor correction circuit 10 and a control circuit therefor 20. The rectified AC voltage is provided to boost inductor L. A PFC switch Q1 is coupled in series with the inductor and across the output of the bridge rectifier (BR) after the inductor L. The boost diode BD is coupled in series with the inductor L and the output capacitor COUT is coupled to the output of the boost converter circuit in a known fashion. The voltage across capacitor COUT is the DC bus voltage and is provided to the LOAD.
The control circuit 20 is used to control the PFC circuit 10. In the control circuit 20, the DC bus voltage V_DC is provided to an analog to digital (A/D) converter 12 which also receives the current I_IN of the inductor L as sensed by a resistor RI or by other sensing means, and the rectified AC input voltage V_IN. The A/D converter 12 produces three outputs comprising digital implementations of the DC bus voltage V_DC (VdcFdb), the input voltage V_IN (V_IN′) and the inductor current I_IN (I_IN′). While a digital implementation is illustrated, it is noted that substantially the same process is performed in a totally analog circuit as well.
A ramp generator 14 receives DC reference voltage Vdc_Ref. The output of the ramp generator 14 is provided to a difference circuit 16 in which the digitized DC bus voltage VdcFdb is subtracted from the ramp voltage. This is fed to a voltage regulator which may comprise a proportional integrator (PI) controller 18. The output of the PI controller 18 is fed to a multiplier circuit 22 wherein the voltage output from the voltage regulator (PI controller 18) and the input voltage V_IN′ are multiplied. This results in a current reference PFC signal IREF_PFC, from which the inductor current I_IN′ is subtracted in a difference stage 24. The output of this difference stage 24 is fed to a current regulator comprising a PI controller 26. The output of the PI controller 26, CAOut, is fed to a comparator 28 wherein the PWM signal is generated by comparing an oscillator signal, typically a ramp or sawtooth signal 30 generated by an oscillator with the output (CAOut) of the controller 28. The output, PWM_PFC, controls the duty cycle of the PWM signal provided to control the switch Q1 and thereby control the power factor correction. A PFC enable signal 32 may be provided to blocks 14, 18, 26 and 28 to disable PFC operation from another circuit.
As noted above, the control circuit 20 illustrated in FIG. 1, while a digital circuit, is substantially similar to an analog circuit used to control PFC. The digital PFC control circuit 20, however, has certain inherent limitations, in particular, based on the fact that it is a digital circuit. FIG. 3 illustrates that the key to PFC control is the current regulation loop, which forces the inductor current waveform to track the rectified half wave sinusoidal reference IREF_PFC. This regulation is typically performed entirely by PI controller 26. PI controllers are typically good at regulating signals that have a steady state of a constant DC value, but are not typically useful for regulating a time-varying signal, such as a sinusoidal current, unless the control bandwidth of the controller is very high. In the PFC control setting, however, the inductor current is always changing in a sinusoidal fashion. Thus, there is no steady state signal for the PI controller to regulate. In addition, the sample-hold (S/H) delay that is inherent to the analog to digital (A/D) conversion process introduces further complications.
The S/H delay may be expressed as follows:
                                          H            ⁡                          (              s              )                                =                                                    1                -                                  ⅇ                                                            -                                              T                        s                                                              ·                    s                                                              s                        ≈                          1                              1                +                                                                            T                      s                                        ·                    s                                    2                                                                    ,                            Eq        .                                  ⁢        1.1            where Ts is the sampling period. The approximation indicated above is valid when Ts is sufficiently short. As illustrated in FIG. 4, the longer the sampling period Ts, the larger the phase shift. The phase shift will reduce the margin of the closed loop gain and affect the system stability. In order to maintain the stability of the closed loop control, the gain and bandwidth of the PI controller 26 should be reduced. However, as noted above, when the gain and bandwidth of the PI controller 26 are reduced, the PI controller will not be able to track the sinusoidal reference signal which will result in higher distortion and a lower power factor. FIGS. 5A and 5B illustrate test waveforms of a bridgeless PFC circuit using conventional digital control and a 20 kHz A/D sampling rate under heavy load (5A) and light load (5B), respectively. As illustrated, there is significant distortion and oscillation in the current waveforms. The distortion is such that the circuit would not meet the EN61000-3-2 Class A harmonic standard.
Further, the PWM stage 28, itself, may cause problems. PFC modeling theory indicates that the PWM stage has a sample-data effect similar to the sample and hold (S/H) delay in digital control discussed above. Thus, even if an analog control circuit is used, when the PWM carrier frequency is too low, the current control performance may still be undesirable. However, in an analog control circuit, the PWM carrier frequency normally is relatively high, typically in the range of 50 kHz to 100 kHz. Thus, the current loop bandwidth can be designed to be around 5 kHz-10 kHz. At this frequency, the current can be controlled to have relatively good tracking of the sinusoidal reference. That is, the limitations of the analog control circuit are somewhat “disguised.” Nevertheless, at high switching frequencies, undesirable switching losses and EMI noise are present even in analog control circuits. Digital control may address these problems, but brings its own problems, as noted above.
One solution has been to use a higher sampling rate in the A/D process, which results in a smaller Ts and reduces the phase shift. While this improves current waveform control, it significantly increases the cost of the digital IC since high speed A/D conversion is necessary along with high computation power in the digital processor. While the problems discussed above are discussed with reference to the conventional boost PFC circuit 10 of FIG. 1, it is noted that the same problems arise using the bridgeless PFC circuit 10a of FIG. 2, for example.
FIG. 1A illustrates another embodiment of a PFC control circuit that utilizes partial mode PFC and PWM blanking as is described, for example, in U.S. patent application Ser. No. 11,269,377 entitled HIGH FREQUENCY PARTIAL BOOST POWER FACTOR CORRECTION CONTROL CIRCUIT AND METHOD filed Nov. 4, 2005 as a continuation in part of application Ser. No. 11/165,939 filed Jun. 24, 2005, entitled HIGH FREQUENCY PARTIAL BOOST POWER FACTOR CORRECTION CONTROL CIRCUIT AND METHOD which claims the benefit and priority of Provisional Application Ser. No. 60/583,752 filed Jun. 28, 2004, entitled A NEW HIGH-FREQUENCY PARTIAL BOOST POWER-FACTOR-CORRECTION CONTROL METHOD, the entire disclosure of each of which is hereby incorporated by reference herein. A PWM blanking algorithm is further described therein and also in Provisional Application Ser. No. 60/626,113 filed Nov. 8, 2004 entitled PWM BLANKING ALGORITHM IN HIGH FREQUENCY PARTIAL PFC and Provisional Application Ser. No. 60/626,112 filed Nov. 8, 2004 entitled DC BUS VOLTAGE CONTROL METHOD IN HIGH-FREQUENCY PARTIAL PFC, the entire disclosures of which are hereby incorporated by reference herein.
In partial mode PFC, a partial PFC controller 90 is fed the instantaneous rectified AC input voltage and the instantaneous DC bus voltage and compares the two. When the rectified AC input voltage (V_IN) is less than the DC bus voltage (V_DC), partial PFC controller 90 provides a signal to the PWM comparator 28 to enable the PWM comparator, thereby providing PWM signals to control the on time of switch Q1. When V_IN is greater than V_DC, that is, when the rectified AC input voltage is greater than the DC input voltage, PWM switching of the switch Q1 is not necessary for many applications, and therefore the generation of PWM switching signals is disabled. Partial PFC controller 90 provides a shutdown signal to the PWM comparator 28 to disable the PWM operation and accordingly switch Q1 is maintained in an off state. Such partial mode PFC is useful since PFC is not necessary in some applications and thus it is advantageous to interrupt it under certain conditions. However, while PWM operation is active the same problems arise with regard to distortion in waveforms as discussed below.
An example of a PFC circuit utilizing partial mode PFC is illustrated in FIG. 1A. The circuit of FIG. 1A is substantially similar to that of FIG. 1 except for the inclusion of the partial PFC controller 90. Thus, common elements of the circuit of FIG. 1A are labeled with the same reference numerals as in FIG. 1. FIG. 5C illustrates waveforms for convention full PFC control circuits and the Partial PFC control circuit suggested in FIG. 1A, respectively. Further, FIGS. 5D and 5E illustrate the advantage that partial mode PFC provides over full PFC with regard to Power Factor and Efficiency. FIG. 5F further illustrates the improved EMI affects provided by partial mode PFC as compared to full boost PFC. FIG. 5G further illustrates the improvement provided by partial mode PFC when compared to full boost PFC with regard to EN61000-3-2 Class A harmonic standard. Thus, there are several advantages of using partial PFC, however, the sinusoidal waveform provided using partial mode PFC has the same distortion problems as the conventional circuit of FIG. 1, for example.
Thus, it is desirable to provide an alternative digital control circuit and method that avoids the problems mentioned above.